Logic and Physical Synthesis Methodology for High Performance VLIW/SIMD DSP Core

We describe logic and physical synthesis methodology to achieve timing closure on a high-end VLIW/SIMD DSP processor core. The design comprises of approximately 200,000 placeable instances. The target frequency goal was to achieve 250 MHz in 130 nm technology. The VLIW/SIMD DSP is described using TIE (Tensilica Instruction Extension) language, which is a Verilog-like language for description of Instruction Set Architecture (ISA) extensions. The synthesizable Verilog (or VHDL) is generated using TIE Compiler. TIE Compiler automatically generates complex hardware structures such as multi-ported register files and pipeline management logic. This empowers a designer to easily add custom instructions to suit the target application. However, this also leads to physical design challenges. For example, the DSP core has 7-stage pipeline, 160-bit VLIW datapath comprising of ALU, MAC, and SHIFT units, a 160bit wide multi-ported register file with 16 entries. This leads to complex bypassing logic, which results in a highly congested design. The traditional flow of using synthesis followed with placement and routing lead to a serious timing convergence issue. The use of Physical Compiler helped close the timing gap. In particular, the best results were found using timing driven congestion with high map effort compile for gates-to-placed-gates flow. One of the major challenge is the turnaround time which can be anywhere from few days to a week depending on the speed of the compute servers. In this paper, we describe the gates-to-placed-gates based Physical Compiler methodology that enabled our team to achieve the target frequency.